1. Technical Field
This disclosure relates to switching voltage regulators and more particularly to architectures of feedback voltage regulators, for example, to supply microprocessors.
2. Description of the Related Art
CPUs for PCs, workstations and servers typically need very sophisticated supply control mechanisms. These power supplies typically must meet high precision requirements both in stand-by conditions as well as in conditions of load transients. These requirements led to identify the well known architectures of multi-phase buck regulators as the most appropriate to this objective.
In order to effectively respond to very fast and large load transients (for CPU, up to 100 A in 50 ns) these converters typically employ nonlinear controls that are enabled in presence of load transients and turn on simultaneously all the available phases for sustaining the output voltage. These nonlinear systems advantageously reduce the response time by reacting in an “aggressive” manner to the load transient. Moreover, the multi-phase topologies typically have control mechanisms for limiting the unbalancing of phase currents thus facilitating thermal balancing and preventing excessive stresses of components of the power stage (power MOS and inductors).
A basic block diagram of a typical three-phase buck system, disclosed in U.S. Patent application US2012/0161741, is shown in FIG. 1.
With the evolution of microprocessors and the needs of power saving, also load requirements of microprocessors have changed. In the past, it was assumed that the worst case response was the response with the maximum load step and with the minimum current rise time. Nowadays, microprocessors are allowed to have short load transients with various load steps and with various rise times (Trise). In presence of these small load requests, controllers of the output voltage ideally should provide the same precision and the same efficiency as for full load responses.
Nonlinear systems are affected by drawbacks during these small load requests. Indeed, they typically have a fixed triggering threshold and may abruptly turn on all the available phases of the controller. Therefore, nonlinear systems may not act when the load request is small in respect to the threshold or may act such to make the system respond in an aggressive fashion by turning on all the phases even when it was not necessary. The effect of this nonlinear control is even more evident when the load requests are close to the triggering threshold of the nonlinear system. In these cases, the nonlinear system may respond or even not react at all to small variations giving an undesired response of the load transient. In tests carried out in these conditions, with repeated load transients, large swings of the output voltage exceeding specifications of the regulated voltage were allowed.
There are different solutions for adapting the speed and the response to load transients.
Control methods for adapting the response to load transients are implemented by the so-called COT (Constant-On-Time) voltage regulators, that are regulators in which the on time of switches is constant. As it is well known, in these controllers, the high side MOS is turned on for a defined time determined by a combination of the output voltage VOUT, of the input voltage VIN and of the switching frequency FSW.
Classic constant-on-time voltage regulators that use a comparator for determining the turn on time, are burdened by noise on the feedback line that cause jitter that may exceed the limits fixed by specifications. Moreover, in high frequency designs, with a purely ceramic output capacitive filter, they typically employ the use of a function called “Virtual ESR” that uses the information about the phase current for amplifying the information ripple available at the comparator. Sometimes the signal-to-noise ratio of the ripple of the phase current may cause the same effects caused by jitter as mentioned above.
The published patent application US 2005/0184717 discloses a voltage regulator—shown in FIG. 2—that uses the error amplifier EA for increasing or decreasing the nominal switching frequency of the system, given by IOSC. At each clock pulse generated by the oscillator, the system turns on the phase of the regulator for a fixed duration (constant TON). When the system is stable, the mean output current of the error amplifier EA is null; when a load is added, the output drops and the output current of the error amplifier increases thus causing an increase also of the turn on frequency of the system. If the output of the system increases in respect to the regulated value, for example during a load decrease, the current of the error amplifier becomes negative and thus the frequency of the system decreases. In this prior document, the error amplifier is used for increasing or decreasing the switching frequency during transients. If the generated on time TON is not the correct time for a regulation with the nominal switching frequency, the amplifier may saturate (remain clamped down by the block CLAMP) and may try to correct the switching frequency. In this case it would contribute to the regulation by bypassing the compensation network of the terminal COMP and the stability of the system would be compromised.
The published patent application US 2008/0024104 discloses a constant-on-time voltage regulator—shown in FIG. 3, having a control circuit implementing a pulse-frequency modulation (PFM) control using a voltage-controlled oscillator (VCO). The loop gain, and thus the stability of the system, depends on the regulated voltage to be delivered.
In power supply systems for microprocessors, in which the reference voltage may often vary for adapting the supply voltage to changed working conditions of the microprocessor, instability problems may arise.